As processor speeds continue to increase, memory system designers are under increasing pressure to create memory devices that can input and output data at increasingly faster rates. As such, new memory system designs are constantly being proposed, tested and, if satisfactory, manufactured.
Double data rate (DDR) synchronous dynamic random access memory (SDRAM) devices are a relatively new form of memory device that was designed to help bridge the gap between processor and memory speeds. During read operations, DDR SDRAM devices return a data clock signal (or data strobe) along with the data, and this data clock signal is used to clock the data into the processor (or into a memory controller attached to the processor). The strobe is typically supplied at two times the rate of the system clock, hence the name DDR. These memories differ from conventional memory systems, which rely on the system clock to latch data received during read operations. Similarly, during write operations the data strobe is used to signify the arrival of the data to be written into the DDR SDRAM.
Designing a DDR SDRAM and an interface for the DDR SDRAM, as well as other high speed memory devices currently being developed, is a complex, time consuming and expensive process. Clock skews may adversely effect data and address eyes (i.e., the short period of time in which the data and address information is reliable/valid). If the skew is large enough, a clock edge that is used to latch the data can move from the center of the data eye into a transitional region or into another data eye. This may cause spurious data to be used during read or write operations. In addition, voltage margins may adversely effect the operation of the DDR SDRAM and its power consumption. These problems must be addressed prior to the final implementation and packaging of the new memory product.
Initially, the new memory device, which may comprise memory, a controller, power supply, and other address, timing and control logic/circuitry must be designed and prototyped. The prototype is then tested and evaluated. Problems such as clock skew, for example, are investigated. Proposed solutions are incorporated in a redesign. The newly re-designed device is prototyped, tested and evaluated until satisfactory results are achieved. This process is expensive and time consuming. For each re-design, new control, timing and address logic may be required, designed, manufactured and tested. Likewise, supply and reference voltages may also be redesigned, manufactured and tested. Prior versions of the device are scrapped. As can be appreciated, the development of new memory devices takes a substantial amount of time, is expensive, wasteful and inefficient.
Accordingly, there is a desire and need for a mechanism for testing and evaluating memory technology in a quick, flexible, efficient and inexpensive manner.